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CMOS ASYNCHRONOUS FIFO 32,768 x 9
Integrated Device Technology, Inc.
IDT7207
FEATURES:
* 32768 x 9 storage capacity * High-speed: 15ns access time * Low power consumption -- Active: 660mW (max.) -- Power-down: 44mW (max.) * Asynchronous and simultaneous read and write * Fully expandable in both word depth and width * Pin and functionally compatible with IDT720x family * Status Flags: Empty, Half-Full, Full * Retransmit capability * High-performance CMOS technology * Military product compliant to MIL-STD-883, Class B * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7207 is a monolithic dual-port memory buffer with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. Data is toggled in and out of the device through the use of the Write (W) and Read (R) pins. The devices 9-bit width provides a bit for a control or parity at the user's option. It also features a Retransmit (RT) capability that allows the read pointer to be reset to its initial position when is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes. The IDT7207 is fabricated using IDT's high-speed CMOS technology. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate buffering, and other applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
RT
FUNCTIONAL BLOCK DIAGRAM
WRITE CONTROL
DATA INPUTS (D 0 -D 8 )
W
WRITE POINTER
RAM ARRAY 32,768 x 9
READ POINTER
THREESTATE BUFFERS DATA OUTPUTS (Q 0 -Q 8 )
RS
R
READ CONTROL
RESET LOGIC FLAG LOGIC
EF FF
FL/RT
XI
EXPANSION LOGIC
XO/HF
3140 drw 01
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-3140/2
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
D8 D3 D2 D1 D0
XI FF
Q3 Q8 GND NC R Q4 Q5
3140 drw 02
Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P28-1 D28-1
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc D4 D5 D6 D7
FL/RT RS EF XO/HF
INDEX D2 D1 D0
XI FF
Q7 Q6 Q5 Q4 R
14 15 16 17 18 19 20
Q0 Q1 NC Q2
5 6 7 8 9 10 11 12 13
32 31 30 1
4 3 2
D3 D8 W NC Vcc D4 D5
PIN CONFIGURATIONS
J32-1 & L32-1
29 28 27 26 25 24 23 22 21
D6 D7 NC
FL/RT RS EF XO/HF
Q7 Q6
3140 drw 03
DIP TOP VIEW
PLCC/LCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to + 7.0 Military -0.5 to +7.0 Unit V
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCCM VCCC GND VIH
(1)
Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input High Voltage Military Input Low Voltage Commercial and Military
Min. 4.5 4.5 0 2.0 2.2 --
Typ. 5.0 5.0 0 -- -- --
Max. 5.5 5.5 0 -- -- 0.8
Unit V V V V V V
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to + 125 50
-55 to +125 -65 to +135 -65 to +155 50
C C C mA
VIH(1) VIL(1)
NOTE: 3140 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
3140 tbl 02
DC ELECTRICAL CHARACTERISTICS FOR THE 7207
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5.0V10%, TA = -55C to +125C)
IDT7207 Commercial tA = 15, 20, 25, 35, 50 ns Symbol ILI(1) ILO
(2)
IDT7207 Military tA = 20, 30, 50 ns Min. -1 -10 2.4 -- -- -- -- Typ. -- -- -- -- -- -- -- Max. 1 10 -- 0.4 150
(4)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOH = -2mA Output Logic "0" Voltage IOL = 8mA Active Power Supply Current Standby Current (R=W=RS=FL/RT=VIH) Power Down Current (All Input = VCC - 0.2V)
Min. -1 -10 2.4 -- -- -- --
Typ. -- -- -- -- -- -- --
Max. 1 10 -- 0.4 120 8
(4)
Unit A A V V mA mA mA
3140 tbl 04
VOH VOL ICC1 ICC2
(3) (3)
12
25 12
ICC3(L)(3)
NOTES: 1. Measurements with 0.4 VIN VCC. 2. R VIH, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open (only capacitive loading). 4. Tested at f = 20MHz.
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
Com'l 7207L15 Symbol fS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRTR tRTC tRT tRTS tRSR tEFL tRTF tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tXOL tXOH tXI tXIR tXIS Parameters Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width(2) Read LOW to Data Bus LOW(3) Write HIGH to Data Bus Low-Z Data Valid from Read HIGH Read HIGH to Data Bus High-Z(3) Write Cycle Time Write Pulse Width(2) Write Recovery Time Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width(2) Reset Set-up Time
(3) (3, 4)
Com'l & Mil. 7207L20 -- 30 -- 10 20 5 5 5 -- 30 20 10 12 0 30 20 20 10 30 20 20 10 -- -- -- -- -- 20 -- -- -- -- 20 -- -- 20 10 10 33.3 -- 20 -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- -- -- -- -- 30 30 30 20 20 -- 20 20 30 30 -- 20 20 -- -- --
Com'l 7207L25 -- 35 -- 10 25 5 5 5 -- 35 25 10 15 0 35 25 25 10 35 25 25 10 -- -- -- -- -- 25 -- -- -- -- 25 -- -- 25 10 10 28.5 -- 25 -- -- -- -- -- 18 -- -- -- -- -- -- -- -- -- -- -- -- -- 35 35 35 25 25 -- 25 25 35 35 -- 25 25 -- -- --
Military 7207L30 -- 40 -- 10 30 5 5 5 -- 40 30 10 18 0 40 30 30 10 40 30 30 10 -- -- -- -- -- 30 -- -- -- -- 30 -- -- 30 10 10 25 -- 30 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 40 40 40 30 30 -- 30 30 40 40 -- 30 30 -- -- --
Com'l 7207L35 -- 45 -- 10 35 5 10 5 -- 45 35 10 18 0 45 35 35 10 45 35 35 10 -- -- -- -- -- 35 -- -- -- -- 35 -- -- 35 10 15 22.2 -- 35 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 45 45 45 30 30 -- 30 30 45 45 -- 35 35 -- -- --
Com'l & Mil. 7207L50 Min. Max. Unit -- 65 -- 15 50 10 15 5 -- 65 50 15 30 5 65 50 50 15 65 50 50 15 -- -- -- -- -- 50 -- -- -- -- 50 -- -- 50 10 15 15 -- 50 -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- -- -- -- 65 65 65 45 45 -- 45 45 65 65 -- 50 50 -- -- -- MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3140 tbl 05
Min. -- 25 -- 10 15 5 5 5 -- 25 15 10 11 0 25 15 15 10 25 15 15 10 -- -- -- -- -- 15 -- -- -- -- 15 -- -- 15 10 10
(3)
Max. Min. Max. Min. Max. Min. Max. Min. Max. 40 -- 15 -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- -- -- -- -- 25 25 25 15 15 -- 15 15 25 25 -- 15 15 -- -- --
Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width(2) Retransmit Set-up Time Reset to EF LOW Retransmit LOW to Flags Valid Read LOW to EF LOW Read HIGH to FF HIGH Read Pulse Width after EF HIGH Write HIGH to EF HIGH Write LOW to FF LOW Write LOW to HF Flag LOW Read HIGH to HF Flag HIGH Write Pulse Width after FF HIGH Read/Write LOW to XO LOW Read/Write HIGH to XO HIGH XI Pulse Width(2) XI Recovery Time XI Set-up Time Retransmit Recovery Time
tHFH, tFFH Reset to HF and FF HIGH
NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum are not allowed. 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode.
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure 1
3140 tbl 07
5V
1.1K D.U.T. 680 30pF*
CAPACITANCE(1) (TA = +25C, f = 1.0 MHz)
Symbol CIN(1) COUT
(1,2)
Parameter Input Capacitance Output Capacitance
Condition VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
3140 tbl 08
OR EQUIVALENT CIRCUIT
3140 drw 04
NOTES: 1. This parameter is sampled and not 100% tested. 2. With output deselected.
Figure 1. Output Load *Includes jig and scope capacitances.
SIGNAL DESCRIPTIONS Inputs:
DATA IN (D0-D8) -- Data inputs for 9-bit wide data.
Controls:
RESET (RS -- Reset is accomplished whenever the Reset RS) (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must R W be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before the rising edge of RS and should not RS) change until tRSR after the rising edge of RS RS. WRITE ENABLE (W) -- A write cycle is initiated on the falling W edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a new valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full.
READ ENABLE (R) -- A read cycle is initiated on the falling R edge of the Read Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a high-impedance condition until the next Read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the "final" read cycle but inhibiting further read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL RT) -- This is a dualFL/RT purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device loaded (see Operating Modes). The Single Device Mode is initiated by grounding the Expansion In (XI). The IDT7207 can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 32,768 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode. EXPANSION IN (XI -- This input is a dual-purpose pin. XI) Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy-Chain Mode.
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Outputs:
FULL FLAG (FF -- The Full Flag (FF) will go LOW, inhibiting FF) further write operations, when the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go LOW after 32,768 writes. EMPTY FLAG (EF -- The Empty Flag (EF) will go LOW, EF) inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO HF) -- This is a XO/HF dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a halffull memory. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW
t RS
RS
and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. There will be an XO pulse when the Write pointer reaches the last location of memory, and an additional XO pulse when the Read pointer reaches the last location of memory. DATA OUTPUTS (Q0-Q8) -- Q0-Q8 are data outputs for 9bit wide data. These outputs are in a high-impedance condition whenever Read (R) is in a HIGH state.
t RSC
t RSS
W
t RSR
t RSS
R
t EFL
EF
t HFH , t FFH
HF, FF
3140 drw 05
NOTE: 1. W and R = VIH around the rising edge of RS. Figure 2. Reset
t RC tA
R
t RPW t RR tA t DV DATA t WC
OUT
t RLZ Q 0 -Q 8
t RHZ DATA
OUT
VALID
VALID
t WPW
W
t WR
t DS D 0 -D 8 DATA
IN
t DH VALID DATA
IN
VALID
3140 drw 06
Figure 3. Asynchronous Write and Read Operation
5.05
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITE
IGNORED WRITE
FIRST READ
R
W
t WFF
FF
t RFF
3140 drw 07
Figure 4. Full FlagTiming From Last Write to First Read
LAST READ
W
IGNORED READ
FIRST WRITE
R
t
EF
REF
t
WEF
t DATAOUT
A
VALID
3171 drw 08
Figure 5. Empty Flag Timing From Last Read to First Write
t
RT
RTC
t RT
t RTS
W,R
t RTR
RTF
HF, EF, FF
FLAG VALID
3140 drw 09
NOTE: 1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC. Figure 6. Retransmit
5.05
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
t
WEF
EF
t
R
RPE
3140 drw 10
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
t
FF
RFF
t WPF
W
3140 drw 11
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
W
t RHF
R
t WHF
HF
HALF-FULL OR LESS
MORE THAN HALF-FULL
HALF-FULL OR LESS
3140 drw 12
Figure 9. Half-Full Flag Timing
W
WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION t XOL t XOH
R
t XOL
XO
t XOH
3140 drw 13
Figure 10. Expansion Out
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
XI
XI
t XIR
t XIS
W
WRITE TO FIRST PHYSICAL LOCATION
t XIS READ FROM FIRST PHYSICAL LOCATION
3140 drw 14
R
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single IDT7207 may be used when the application requirements are for 32,768 words or less. The IDT7207 is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). Depth Expansion The IDT7207 can easily be adapted to applications when the requirements are for greater than 32,768 words. Figure 14 demonstrates Depth Expansion using three IDT7207s. Any depth can be attained by adding additional IDT7207s. The IDT7207 operates in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules.
corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two IDT7207s. Any word width can be attained by adding additional IDT7207s (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7207s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15).
USAGE MODES:
Width Expansion Word width may be increased simply by connecting the
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HALF-FULL FLAG) WRITE (W) 9 DATA IN (D) FULL FLAG (FF) RESET (RS)
(HF) READ (R) IDT 7207 9 DATA OUT (Q) EMPTY FLAG (EF) RETRANSMIT (RT)
EXPANSION IN (XI)
3140 drw 15
Figure 12. Block Diagram of 32,768 x 9 FIFO Used in Single Device Mode
HF
HF
18 DATA IN (D) WRITE (W)
9
9
IDT 7207 FULL FLAG (FF) RESET (RS) 9
IDT 7207
READ (R) EMPTY FLAG (EF)
9
RETRANSMIT (RT)
XI
XI
18 DATA
NOTE: 1. Flag detection is accomplished by monitoring the FF, Do not connect any output signals together.
OUT (Q)
3140 drw 16
EF
and HF signals on either (any) device used in the width expansion configuration.
Figure 13. Block Diagram of 32,768 x 18 FIFO Memory Used in Width Expansion Mode
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES TABLE I - RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Mode Reset Retransmit Read/Write
RS RT XI
Internal Status Read Pointer Location Zero Location Zero Increment (1) Write Pointer Location Zero Unchanged Increment (1)
EF
Outputs
FF HF
0 1 1
X 0 1
0 0 0
0 X X
1 X X
1 X X
3140 tbl 09
NOTE: 1. Pointer will Increment if flag is HIGH.
TABLE II - RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Mode Reset First Device Reset all Other Devices Read/Write
RS FL XI
Internal Status Read Pointer Location Zero Location Zero X Write Pointer Location Zero Location Zero X
EF
Outputs
FF
0 0 1
0 1 X
(1) (1) (1)
0 0 X
1 1 X
3140 tbl 10 NOTES: 1. XI is connected to XO of previous device. See Figure 14. 2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
XO W FF
IDT 7207
R EF
D
9
9
FL
9
Q VCC
XI
XO FF
FULL
9
IDT 7207
EF
EMPTY
FL
XI XO FF
9
RS
IDT 7207
EF
FL XI
3140 drw 17
Figure 14. Block Diagram of 98,304 x 9 FIFO Memory (Depth Expansion)
5.05
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IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Q 0 -Q 8
Q 9 -Q 17 ***
Q (N-8)
-Q N
Q 0 -Q 8 IDT7207 DEPTH EXPANSION BLOCK
R, W, RS
Q 9 -Q 17 IDT7207 DEPTH EXPANSION BLOCK ***
Q (N-8) IDT7207 DEPTH EXPANSION BLOCK
-Q N
D 0 -D 8 D 0 -D N D 9 -D N NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13.
D 9 -D 17 *** D 18 -D N D (N-8) -D N
D (N-8) -D N
3140 drw 18
Figure 15. Compound FIFO Expansion
WA
FFA
IDT 7207 IDT 7201A
R
B
EF B HF B
DA 0-8
Q B 0-8
SYSTEM A
SYSTEM B
Q A 0-8
IDT 7207
R
D B 0-8
WB
A
HFA EF A FF B
3140 drw 19
Figure 16. Bidirectional FIFO Operation
DATA IN
W
t RPE
R
EF
t WEF t WLZ DATA OUT tA
t REF DATA VALID
OUT
3171 drw 20
Figure 17. Read Data Flow-Through Mode
5.05
11
IDT7207 CMOS ASYNCHRONOUS FIFO 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
R
t
W
WPF
t RFF
FF
t WFF DATA IN t DATA
OUT A
t
IN
DH
DATA
VALID
t DS DATA
OUT
VALID
3140 drw 21
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
IDT XXXX Device Type X Power XX Speed X Package X Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B Plastic DIP Ceramic DIP Plastic Leaded Chip Carrier Leadless Chip Carrier (Military only) Commercial Only Commercial Only Military Only Commercial Only Access Time (tA) Speed in ns
P D J L 15 20 25 30 35 50 L 7207
Low Power 32,768 x 9 FIFO
3140 drw 22
5.05
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